The present invention relates to an apparatus and a method for analyzing circuit test results, and further a recording medium storing an analytical program for analyzing the circuit test results, which are suitably used for an LSI having memory cells.
Electrical tests for an LSI having memory cells are carried out by an electric testing device. The subject of the electrical test is the memory cells. Specifically, through the electric testing device, certain test data are written into each memory cell on the LSI and thereafter it is checked whether each written datum can be non-defectively read out therefrom.
There are included both inherently defective memory cells and entirely non-defective memory cells in those memory cells as judged to be defective by the electric testing device. Such a memory cell as to be regarded as defective by the testing device notwithstanding its being indeed non-defective is called a pseudo- defective memory cell hereinafter.
In order to distinguish between an actually defective memory cell and a pseudo-defective memory cell among those as judged to be defective memory cells as above, it is necessary to re-examine each of all memory cells as judged to be defective. Such a re-examination requires a great deal of labor.
An address of the memory cell as judged to be defective is obtained from data of the circuit test results, however, it is far difficult to get hold of where the memory cell is positioned on a wafer.